Advance Program
subject to change


Follow this link for a detailed schedule including abstracts of all papers and posters
 

    CONFERENCE-AT-A-GLANCE

Monday, September 27

Registration
7:00 a.m. -
5:00 p.m.

 

Plenary Session
8:30 a.m. -
12:00 noon.

Opening Remarks:
   Thomas Büchner, General Conference Chair
Technical Program Overview:
   Ramalingam Sridhar, Technical Program Chair
Keynote Presentation:
  Alberto Sangiovanni-Vincentelli, Professor, University of California at Berkeley, and Chief Technology Advisor, Cadence Design Systems
Plenary Presentations:
Michael Keating, Fellow, Synopsys Inc.
  Sandra Woodward, Senior Technical Staff Member, PowerEN Processor Chip Technical Lead, IBM Corp.

12:00 noon -
1:00 p.m.

Lunch (on your own)

Technical Sessions
1:00 p.m. -
2:40 p.m.

MA3:
SoC Power Optimization Techniques

MB3:
Analog 1

Embedded Tutorial
2:55 p.m. -
3:45 p.m.

Embedded Tutorial MT1:
A Holistic View on Low Power Design
Thomas Büchner, IBM

Technical Sessions
3:45 p.m. -
5:00 p.m.

MA4:
Low Power SoC Circuits

MB4:
Analog 2

Embedded Tutorial
5:00 p.m. -
6:00 p.m.

Embedded Tutorial MT2:
Low-power SOC implementation: What you need to know
Kaijian Shi, Synopsys

Tuesday, September 28

Registration
7:30 a.m. -
5:00 p.m.

 

Technical Sessions
8:00 a.m. -
9:40 a.m.

TA1:
Multimedia Processing

TB1:
System Level Design Methodologies 1

Technical Sessions
9:55 a.m. -
12:00 noon.

TA2:
Design

TB2:
System Level Design Methodologies 2

12:00 noon. -
1:30 p.m.

Luncheon
Luncheon Speaker:
P.R.Mukund, President and CEO, NanoArk Corp.

Technical Sessions
1:30 p.m. -
4
:15 p.m

TA3:
Low Power Design

TB3:
Reconfigurable Systems

4:15 p.m. -
6:00 p.m.

Poster Session
with Reception

6:00 p.m. -
7:30 p.m.

Panel Discussion:
SOC Efficiency - Will Software or Hardware Dominate?
Moderator: Andrew Marshall, Texas Instruments

Wednesday, September 29

Registration
8:00 a.m. -
3:30 p.m.

 

Plenary Session
8:00 a.m. -
8:50 a.m.

Plenary Talk:
What You Need to Know About Patent Litigation
Jo Dale Carothers, Covington & Burling LLP

Technical Sessions
8:50 a.m. -
10:05 p.m.

WA1:
Communication Circuits and Systems

Embedded Tutorial WT1
Quality-driven SoC Architecture Synthesis for Embedded Applications
Lech Jóźwiak, Eindhoven University of Technology

Technical Sessions
10:20 a.m. -
12:25 p.m.

WA2:
Network on Chip 1

WB2:
Embedded Memory and Systems 1

12:00 noon -
1:00 p.m.

Lunch (on your own)

1:00 p.m. -
2:40 p.m.

WA3:
Network on Chip 2

WB3:
Embedded Memory and Systems 2

2:40 p.m.

Conference ends